This invention relates to plasma display panel and, more particularly, to a structure of a plasma display panel for increasing an offset margin for assemblage and a controlling method used therein.
The plasma display panel has various attractive features. The plasma display panel is thin, free from flicker and large in contrast. It is easy to provide a wide display area, and the viewing angle is large. The plasma display panel is promptly responsive to an image signal, and a vivid full color image is produced in the wide display area. The plasma display panel is, by way of example, used as an image display unit of a computer system.
The plasma display panel is broken down into two categories. One of the categories is called as xe2x80x9calternating current plasma display panelxe2x80x9d. The alternating current plasma display panel has electrodes covered with a dielectric layer, and alternating current is applied between the electrodes so as to generate discharge in the discharge gas. The other category is called as xe2x80x9cdirect current plasma display panelxe2x80x9d, and the electrodes are directly exposed to discharge gas. Direct current is applied to the electrodes, and the electrode generates discharge. The dielectric layer protects the electrodes of the alternating current plasma display panel from the ion bombardment, and is durable rather than the electrodes of the direct current plasma display panel.
The alternating current plasma display panel is further broken down into two sub-categories, i.e., refresh type and memory type. The alternating current plasma display panel varies the illuminance together with the repetition of discharge during a frame. The discharge takes place at each pulse, and the repetition of discharge is proportional to the number of pulses applied to the electrode during the frame. The memory type alternating current plasma display panel can adjust the number of pulses applied to each of the electrodes to an arbitrary value. On the other hand, the refresh type alternating current plasma display panel decreases the displaying time and, accordingly, the repetition of discharge on each scanning line inversely to the displaying capacity. For this reason, the memory type alternating current plasma display panel widely varies the illuminance of an image rather than the refresh type alternating current plasma display panel, and is appropriate to a wide display area. On the other hand, the refresh type alternating current plasma display panel is appropriate to a narrow display area.
A typical example of the memory type alternating current plasma display panel has discharging space between two substrate structures, and three kinds of electrodes are formed on the inner surfaces of the two substrate structures. Two kinds of electrodes are arranged on one of the substrate structures, and are used for sustain discharge. The remaining electrodes are patterned on the other substrate structure, and are used for write-in discharge together with one of the two kinds of electrodes.
FIG. 1 illustrates a pixel of the prior art memory type alternating current plasma display panel. The prior art memory type alternating current plasma display panel largely comprises two substrate structures 1/2 and spacers 3 for creating discharging space 4 between the substrate structures 1 and 2. The substrate structure 1 provides a display area, and an image is produced therein.
The substrate structure 1 includes a front transparent panel 1a, a scanning electrode 1b formed on the inner surface of the front transparent panel 1a, a sustain electrode 1c formed on the inner surface in parallel to the scanning electrode 1b, a dielectric layer 1d covering the scanning/sustain electrodes 1b/1c and a protective layer 1e laminated on the dielectric layer 1d. On the other hand, the other substrate structure 2 includes a back panel 2a, a data electrode 2b extending on the inner surface of the back panel 2a in perpendicular to the scanning/sustain electrodes 1b/1c, a dielectric layer 2c covering the data electrode 2b and a phosphor layer 2d laminated on the dielectric layer 2c. The discharging space 4 is filled with discharge gas such as helium, neon, xenon or gaseous mixture thereof, and the spacer 3 defines the pixel. The discharge gas radiates ultra-violet light, and the phosphor layer 2d converts the ultra-violet light to visible light 5. The visible light 5 passes through the front panel 1a, and forms a part of an image produced in the display area. The protective layer 1e is formed of magnesium oxide, and prevents the dielectric layer 1d from bombardment during the discharge.
The prior art memory type alternating current plasma display panel produces an image as follows. The pixel shown in FIG. 1 is required to emit the visible light 5. Firstly, a scanning pulse signal is applied between the scanning electrode 1b and the data electrode 2b, and the pulse height is larger than the threshold of discharge. The scanning pulse signal causes the discharge gas to initiates the discharge, and positive/negative charges takes place. The phosphor layer 2d converts the ultra-violet light to the visible light 5, and the visible light 5 forms a part of the image. The positive charge and the negative charge are attracted to the scanning electrode 1b and the data electrode 2b, and are accumulated on the inner surfaces of the substrate structures 1/2, respectively. The accumulated wall charges are inverse in polarity to the potential levels on the scanning/data electrodes 1b/2b, and reduce the effective potential difference between the scanning electrode 1b and the data electrode 2b. As a result, even though the scanning pulse signal is still applied between the scanning electrode 1b and the data electrode 2b, the pixel can not continue the discharge.
The wall charges are obstacle to continuation of the discharge. In order to eliminate or neutralize the wall charge, sustain pulse signal is alternately applied between the scanning electrode 1b and the sustain electrode 1c. Although the sustain pulse signal is lower than the threshold of discharge, the sustain pulse signal is identical in polarity with the wall charge on the substrate structure 1, and the wall charge causes the effective potential difference to exceed over the threshold of discharge. For this reason, the discharge is continued during the alternation of the sustain pulse signal between the scanning electrode 1b and the sustain electrode 1c. This is the memory function.
In this situation when the wall charge is eliminated or neutralized, the pixel stops the discharge. An erase pulse signal is applied to either scanning or sustain electrode 1b/1c. Then, the pixel can not continue the discharge, and the visible light is extinguished.
The pixels are arranged in rows and columns as shown in FIG. 2, and forms a display area 6. Circles represent the pixels, respectively. The scanning electrodes Sc1, Sc2, . . . and Scj are paired with the sustain electrodes Su1, Su2, . . . and Suj, respectively, and the scanning/sustain electrode pairs Sc1/Su1, Sc2/Su2, . . . and Scj/Suj are associated with the rows of pixels, respectively. On the other hand, data electrodes Da1, Da2, Da3, Da4, . . . , Dak-1 and Dak extend in perpendicular to the scanning/sustain electrode pairs Sc1/Su1 to Scj/Suj, and are respectively associated with the columns of pixels. The phosphor layers 2d are colored in the three primary colors, i.e., red, green and blue, and a color image is produced on the display area 6.
The pixels are controlled as shown in FIG. 3. Each frame is divided into plural sub-fields SF1 to SF6, and each sub-field SF1 to SF6 is further divided into a preliminary discharge period A, an erasing period B, a write-in discharge period C and a sustain discharge period D1/D2/D3/D4/D5/D6. The sustain discharge period D1 is continued for T, and the sustain discharge periods D2 to D6 are successively decreased to T/2, T/4, T/8/T/16 and T/32.
All the pixels are discharged in the preliminary discharge period A, and stop the preliminary discharge in the erasing period B. The scanning pulse signal is sequentially supplied to the scanning electrodes Sc1 to Scj in the write-in discharge period C, and line L1 represents the signal application timing in the write-in discharge period C. Certain pixels to be fired are selected from the pixel array during the write-in discharge period C. Upon completion of the application of the scanning signal, the sustain pulse signal is alternately applied to all the scanning/sustain electrode pairs so as to emit the visible light from the selected pixels. The sustain discharge period is reduced at xc2xdn, and a combination of the sustain discharge periods D1 to D6 determines the illuminance of each pixel. Thus, the prior art control method shown in FIG. 3 achieves a gradation of 26.
The potential levels on the sustain/scanning/data electrodes are varied as shown in FIG. 4. A preliminary discharge pulse signal PS1 is applied to all the sustain electrodes Su1 to Suj in the preliminary discharge period A, and all the pixels are fired. An erasing pulse signal PS2 is applied to the scanning electrodes S1 to Sj in the erasing period B. As a result, active particles are produced, and the wall charges are accumulated. This results in that the pixels become promptly responsive to a scanning pulse signal PS3.
The scanning pulse signal PS3 is sequentially applied to the scanning electrodes S1 to Sj, and a data pulse signal PS4 are selectively applied to the data electrodes Da1 to Dak. When the scanning pulse signal PS3 and the data pulse signal PS4 are concurrently applied to a scanning electrode and a data electrode, a pixel defined by the scanning electrode and the data electrode is fired, and enters into the write-in state. This means that the wall charges take place in the fired pixel.
A sustain pulse signal PS5 is alternately applied to the sustain electrodes Su1 to Suj and the scanning electrodes Sc1 to Scj, and the pixels in the write-in state are continuously fired.
The pixels have been miniaturized, and, accordingly, the manufacturer has increased the scanning/sustain electrode pairs and the data electrodes of the prior art memory type alternating current plasma display panel. The prior art memory type alternating current plasma display panel with increased scanning/sustain electrode pairs requires the write-in discharge period C longer than the write-in discharge period for the standard memory type alternating current plasma display panel, and each sub-field is prolonged. If the manufacturer keeps the time period for each sub-field constant, it is necessary to make the scanning pulse signal narrower, and the wall charge in a selected pixel is too little to sustain the firing in the sustain discharge period.
When the manufacturer is expected to increase the gradation, each frame requiresxe2x80x94requires the sub-fields more than those of the standard memory type alternating current plasma display panel, and the time period for each sub-field is shrunk. As a result, the scanning pulse signal PS2 is narrowed, and certain selected pixels are misfired due to insufficient wall charge.
The total time TC for the write-in discharge periods C in each frame is expressed as
xe2x80x83TC=Twxc3x97Lnxc3x97Sfxe2x80x83xe2x80x83equation 1
where Tw is the pulse width of the scanning pulse signal PS3, Ln is the number of the scanning electrodes and Sf is the number of the sub-fields. When the frame frequency is adjusted to f, the time for each frame is given by equation 2.
1/f=TC+Txcex1xe2x80x83xe2x80x83equation 2
where Txcex1 is the total time period of the preliminary discharging period A, the erasing period B and the sustain discharge period D. When the number of scanning electrodes is increased or the number of sub-fields is increased, the total time period TC is prolonged. On the other hand, when the frame frequency is increased, the time period for each frame 1/f is shrunk, and the total time period Txcex1 is forced to be shorter. If the manufacturer reduces the sustain discharge period D, the pixels can not achieve a target illuminance. For this reason, the manufacturer usually decreases the sub-fields, and, accordingly, reduces the gradation.
Thus, the prior art controlling method shown in FIG. 3 reaches a technical barrier. M. Uchidoi et al propose an improvement in xe2x80x9cPanel Design and Driving Method of 40-in. Diagonal AC Plasma Displaysxe2x80x9d, IDW""96, pages 291 to 294. Uchidoi et al divide the electrodes to be scanned into two groups, and the two groups are concurrently scanned for selectively changing the pixels to the write-in state. As a result, the total write-in discharge period is reduced to a half of the above described prior art memory type alternating current plasma display panel. The controlling sequence proposed by Uchidoi et al allows the manufacturer to increase the scanning electrodes, the sub-fields and/or the frame frequency without reduction of the gradation.
FIG. 5 illustrates the memory type alternating current plasma display panel proposed by Uchidoi et al. Small ellipses represent pixels, respectively, and are arranged in rows and columns. The rows of pixels are divided into two groups 11 and 12, which are hereinbelow referred to as xe2x80x9cupper group 11xe2x80x9d and xe2x80x9clower group 12xe2x80x9d. Scanning electrodes Sc1 to Scj are divided into two groups Sc1/Sc2/ . . . /Scj/2 and Scj/2+1/ . . . /Scj, and are respectively paired with sustain electrodes Su1/Su2/ . . . /Suj+2, Suj/2+1/ . . . /Suj. The scanning/sustain electrode pairs Sc1/Su1 to Scj/Suj are also divided into two groups Sc1/Su1 . . . Scj/2/Suj/2 and Scj/2+1/Suj/2+1 . . . Scj/Suj, and are respectively associated with the rows of pixels in the upper group 11 and the rows of pixels in the lower group 12. Two groups of data electrodes Du1 to Duk and Dd1 to Ddk are prepared for the upper group 11 and the lower group 12, and are respectively associated with the columns of pixels in the upper group 11 and the columns of pixels in the lower group 12.
The prior art memory type alternating current plasma display panel shown in FIG. 5 produces an image through the following control sequence. FIG. 6 illustrates the control sequence. Each sub-field is divided into the preliminary discharge period A, the erasing period B, the write-in discharge period C and the sustain discharge period D.
A preliminary discharge pulse signal PS11 is applied to all the sustain electrodes Su1 to Suj in the preliminary discharge period A, and an erasing pulse signal PS12 is applied to all the scanning electrodes Sc1-Scj in the erasing period B. The upper group 11 and the lower group 12 are concurrently scanned with a scanning pulse signal PS13 in the write-in discharge period C, and a data pulse signal PS14 is selectively applied to the data electrodes Du1 to Duk and the data electrodes Dd1 to Ddk.
In detail, the scanning pulse signal PS13 is concurrently applied to the first scanning electrode Sc1 of the upper group 11 and the first scanning electrode Scj/2+1 of the lower group 12, and the other scanning electrodes of the upper group 11 and the other scanning electrodes of the lower group 12 are sequentially scanned with the scanning pulse signal PS13. Finally, the scanning electrode Scj/2 of the upper group 11 and the scanning electrode Scj of the lower group 12 are concurrently scanned with the scanning pulse signal PS13. Pixels concurrently applied with the scanning pulse signal PS13 and the data pulse signal PS14 enter into the write-in state. Thus, the selective write-in is concurrently carried out for the upper group 11 and the lower group 12.
A sustain pulse signal PS15 are alternately applied to the sustain electrodes Su1 to Suj and the scanning electrodes Sc1 to Scj in the sustain discharge period.
When each frame consists of six sub-fields SF1 to SF6, the scanning pulse signal PS13 is sequentially applied to the scanning electrodes Sc1 to Scj/2 and Scj/2+1 to Scj as shown in FIG. 7. The scanning pulse signal PS13 is applied to the scanning electrodes Sc1 to Scj/2 as indicated by arrow L2 and to the scanning electrodes Scj/2+1 to Scj as indicated by arrow L3. The arrow L2 is moved in parallel to the arrow L3, and the write-in discharge is completed within a half of the time period consumed by the prior art standard memory type alternating current plasma display panel. Thus, the manufacturer can increase the scanning electrodes of the prior art memory type alternating current plasma display panel and the sub-fields in each frame without sacrifice of the gradation and the quality of image to be produced. However, the manufacturer encounters a problem in the prior art memory type alternating current plasma display panel proposed by Uchidoi in the assemblage between the two-substrate structures.
In detail, the substrate structures 1 and 2 are separately manufactured, and are assembled with one another. In the prior art standard memory type alternating current plasma display panel, the data electrodes Da1 to Dak are shared between all the scanning electrodes Sc1 to Scj. Even if the substrate structures 1/2 are offset from each other, the offset equally affects all the pixels, and the write-in discharging characteristics are not changed among the pixels. However, the prior art memory type alternating current plasma display panel proposed by Uchidoi et al has two groups of data electrodes Du1-Duk and Dd1-Ddk, and the group Du1-Duk is spaced from the other group Dd1-Ddk. If the substrate structure is offset from the other substrate structure, the overlapping area between the scanning electrodes Scj/2 and Scj/2+1 and the data electrodes Du1-Duk/Dd1-Ddk are unevenly varied, and the pixels on both sides of the boundary between the pixel groups 11 and 12 differently vary the write-in discharging characteristics as described hereinbelow in detail.
FIG. 8 shows one of the pixels incorporated in the prior art memory type alternating current plasma display panel proposed by Uchidoi et al. A spacer 20 is patterned into a lattice configuration, and defines a rectangular parallelopiped space 21 assigned to the pixel. A scanning electrode 22 and a sustain electrode 23 extend across the pixel in parallel to each other, and a gap 24 takes place between the scanning electrode 22 and the sustain electrode 23. A data electrode 25 projects into the pixel, and the leading end of the data electrode 25 is designated by reference 25a . If the offset varies the leading end 25a from Y0 through Y1, Y2 to Y3, the overlapping area between the scanning electrode 22 and the data electrode 25 is increased, and the scanning electrode 22 and the data electrode 25 start the write-in discharge at lower potential as shown in FIG. 9.
Even if the leading end 25a exceeds over Y3, the minimum potential is not lowered. Therefore, the difference between Y2 and Y3 is the target range for the data electrode 25. FIGS. 10A to 10D illustrate two pixels 21A/21B opposed to each other across the boundary between the two groups 11 and 12. Alphabetic letters xe2x80x9cAxe2x80x9d and xe2x80x9cBxe2x80x9d are added to the references designating the electrodes of the pixel 21A and the references designating the electrodes of the pixel 21B. The scanning electrodes 22A and 22B are corresponding to the scanning electrodes Scj/2 and Scj/2+1.
L1, L2 and Wxe2x80x2 are representative of the projection of the data electrode 25A from the associated scanning electrode 22A, the projection of the data electrode 25B from the associated scanning electrode 22B and the distance between the scanning electrodes 22A and 22B. When the two substrate structures are assembled without any offset margin, the leading ends 25Aa and 25Ba are positioned at Y3, and the projections L1 and L2 are adjusted to L0 as shown in FIG. 10A. The minimum potential is stable at L0.
In order to offer an offset margin Xxe2x80x2 for the assemblage, the data electrode 25A is maintained at L1=L0, and the data electrode 25B is allowed to have the leading end 25Ba at the limit where the data electrode 25B and the scanning electrode 22A are barely prevented from misfiring. The leading end 25Ba is positioned at L2=Xxe2x80x2+L0, and the distance between the leading end 25Ba and the scanning electrode 22A is represented by G min as shown in FIG. 10B.
If the substrate structures are offset from the target position shown in FIG. 10B in the direction of arrow AR21, the data electrode 25A projects from the associated pixel, and the data electrode 25B is retracted into the associated pixel as shown in FIG. 10C. If the substrate structures are widely offset from the target position, the leading end 25Ba projects from the scanning electrode 22B by L0, and the data electrode 25A further penetrates under the sustain electrode 23A so as to have the leading end 25Aa at L1=Xxe2x80x2+L0.
If the distance between the leading end 25Aa/25Ba and the scanning electrode 22B/22A is less than G min, the non-selected pixel is fired. Therefore, the offset margin Xxe2x80x2 for the assemblage is given by equation 3.
Xxe2x80x2={Wxe2x80x2xe2x88x92(L0+G min)}xe2x80x83xe2x80x83equation 3
Thus, the manufacturer encounters the problem in the prior art memory type alternating current plasma display panel proposed by Uchidoi in that the offset margin is extremely small.
It is therefore an important object of the present invention to provide a plasma display panel, which has a large offset margin.
It is also an important object of the present invention to provide a method for controlling the plasma display panel.
To accomplish the object, the present invention proposes to arrange two groups of scanning/sustain electrodes in symmetry with respect to a boundary between the two groups.
In accordance with one aspect of the present invention, there is provided a plasma display panel comprising a plurality of pixel blocks having at least first pixel block and a second pixel block provided on one side of a boundary and the other side of the boundary, a plurality of first scanning electrodes extending in a first direction, a plurality of first sustain electrodes extending in the first direction, respectively paired with the plurality of first scanning electrodes so as to form a plurality of first electrode pairs selectively associated with pixels of the first pixel block and having the inner most first sustain electrode closer to the boundary than the associated innermost first scanning electrode, a plurality of first data electrodes opposed to the plurality of first electrode pairs through a first discharging space, extending in a second direction perpendicular to the first direction and selectively associated with the pixels of the first pixel block, a plurality of second scanning electrodes extending in the first direction, a plurality of second sustain electrodes extending in the first direction, respectively paired with the plurality of second scanning electrodes so as to form a plurality of second electrode pairs selectively associated with pixels of the second pixel block and having the inner most second sustain electrode closer to the boundary than the associated innermost second scanning electrode and a plurality of second data electrodes opposed to the plurality of second electrode pairs through a second discharging space, extending in the second direction and selectively associated with the pixels of the second pixel block.
In accordance with another aspect of the present invention, there is provided a method for controlling a plasma display panel including first sustain electrodes respectively paired with first scanning electrodes so as to form first electrode pairs, second sustain electrodes respectively paired with second scanning electrodes so as to form second electrode pairs, data electrodes opposed to the first electrode pairs and the second electrode pairs for defining a first pixel block and a second pixel block and a boundary opposed to an innermost first sustain electrode and an innermost second sustain electrode closest thereto, and the step comprises the steps of generating a write-in discharge between the data electrodes and the first and second scanning electrodes in such a manner that the write-in discharge sequentially takes place in the first pixel block in a first direction and in the second pixel block in a second direction opposite to the first direction with respect to the boundary and generating a sustain discharge in pixels entered in a write-in state in the previous step.